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parallel processor中文是什么意思

  • 并行處理機(jī)
  • 并行處理器
  • 生代

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  • 例句與用法
  • Content addressable parallel processor
    內(nèi)涵可尋址并行處理機(jī)
  • Amdahl s law governs the speedup of using parallel processors on a problem versus using only one serial processor
    Amdahl法則揭示了使用并行處理器來解決問題與只使用一個(gè)串行處理器來解決問題的加速比。
  • Because the performance of single microprocessor can " t be improved indefinitely due to the limitation of speed and machining technology of chips , so came the massive parallel processors system
    而單處理器計(jì)算機(jī)系統(tǒng)由于處理器運(yùn)算性能受限于芯片速度極限和加工工藝極限，不可能無限提高。于是超大規(guī)模并行處理系統(tǒng)應(yīng)運(yùn)而生。
  • This design can provide a high - speed path to a set of sharc parallel array processor . between this parallel processor and an analog signal acquisition module , the designed system can realize real time transmission
    本設(shè)計(jì)的目的在于為一套sharc并行處理陣列機(jī)提供高速的數(shù)據(jù)通道，使其能與模擬信號(hào)采集模塊進(jìn)行實(shí)時(shí)的數(shù)據(jù)傳輸。
  • Edge is one of the important characteristics of image , and it also is the element of several research areas , like computer vision and pattern identification . cellular neural network ( cnn ) is a parallel processor
    邊緣是圖像中重要的特征之一,是計(jì)算機(jī)視覺、模式識(shí)別等研究領(lǐng)域的重要基礎(chǔ)。細(xì)胞神經(jīng)網(wǎng)絡(luò)( cnn )是一種并行處理器,在圖像處理上有很大的發(fā)展空間。
  • After analyzing the characteristic of the parallel processing system , some problems about design missile - carrying processing system are pointed out ; network in the parallel processing system has become bottleneck and affect the performance of system , so the processing efficiency is analyzed in a multiprocessor system based on cluster - bus and some rules in designing the network in the multiprocessor system are brought out ; genetic algorithm is used for scheduling in the multiprocessor system , and a scheduling algorithm is described to suit arbitrary number of tasks , unequal task processing time , arbitrary precedence relation among tasks and arbitrary number of parallel processor , so that the schedule length will be minimized ; finally , an atr algorithm is mapped to a ring multiprocessor system , and a block diagram using dsp device is constructed . in chapter 4 , the study is performed on real - time system hardware realization of atr . tms320c80 is selected as the kernel processor in multiprocessor system
    為此，對(duì)一種由常用的dsp芯片組成的多處理器系統(tǒng)的處理器利用率進(jìn)行了分析，提出了多處理器系統(tǒng)互連網(wǎng)絡(luò)設(shè)計(jì)的基本原則；本章使用遺傳算法作為實(shí)現(xiàn)多處理器調(diào)度的工具，提出了一種新的任務(wù)調(diào)度算法，該算法主要是為了解決在任務(wù)數(shù)任意、任務(wù)計(jì)算時(shí)間不相等、任務(wù)前趨關(guān)系任意、以及任務(wù)間存在通信和考慮任務(wù)存貯器要求的情況下，如何優(yōu)化任務(wù)在各個(gè)處理器上的分配和執(zhí)行順序，使得多處理器系統(tǒng)總的執(zhí)行時(shí)間最?。蛔詈髮?duì)一個(gè)目標(biāo)識(shí)別算法進(jìn)行了硬件實(shí)現(xiàn)優(yōu)化分析，根據(jù)分析結(jié)果，將算法映射到由dsp芯片組成的環(huán)形網(wǎng)絡(luò)連接的處理器拓?fù)浣Y(jié)構(gòu)上，得到了多處理器系統(tǒng)的原理框圖。
  • On the basis of summarization of the simulating technology of sonar signal , the paper brings forward the mathematics models of radiate noises of ships and torpedo , and simulates in computer ; tests the correctness of some pivotal methods through the simulation , on the basis of which , system scheme being brought out ; a parallel processor with twelve sharcs , combining with parallel processing theory and topographic configuration , is used to realize the algorithm of noise simulation on the basis of research on optimum distribution of algorithm and method of embedment in real time ; at last , gui , realized with vc + + language , is used to set parameters and control the whole parallel system flexibly and conveniently
    本文在綜述聲納信號(hào)模擬技術(shù)的基礎(chǔ)上，首先提出艦船和魚雷輻射噪聲的仿真數(shù)學(xué)模型，并進(jìn)行了計(jì)算機(jī)仿真實(shí)現(xiàn)；通過計(jì)算機(jī)仿真驗(yàn)證了一些關(guān)鍵技術(shù)的正確性，并由此提出系統(tǒng)實(shí)時(shí)實(shí)現(xiàn)方案；構(gòu)造了一個(gè)12個(gè)處理器的并行處理機(jī)? sharc陣列，結(jié)合并行處理理論和sharc陣列的拓?fù)浣Y(jié)構(gòu)研究了有關(guān)仿真算法的最優(yōu)分配及其嵌入整個(gè)聲納系統(tǒng)的方法，實(shí)時(shí)實(shí)現(xiàn)了噪聲模擬算法。最后，使用vc + +語言編寫人機(jī)界面，靈活、方便地進(jìn)行參數(shù)設(shè)置以及對(duì)整個(gè)并行處理系統(tǒng)進(jìn)行控制。
  • In this paper , real time torpedo homing system . which is based on adsp ? 2106x to be discussed . high speed signal parallel processor system is researched , it is made up of intel 80c186eb processor main board and adsp _ 2106x . it can be come true using this system for the accuracy parameter estimation of underwater target which moves on high velocity
    本課題是以高速并行數(shù)字信號(hào)處理芯片adsp ? 2106x為核心，以intel80c186eb微處理器構(gòu)成的cpu模塊為主控板，構(gòu)成完整的高速并行數(shù)字信號(hào)處理機(jī)硬件系統(tǒng)，該硬件系統(tǒng)可以成功地實(shí)現(xiàn)現(xiàn)代魚雷自導(dǎo)的水下高速運(yùn)動(dòng)目標(biāo)參量實(shí)時(shí)精估算法。
  • Finally discusses several class different multi - dsp extended architecture based on vvp platform . chapter 3 analyzes the significance of dynamic reconfiguration of multi - dsp parallel processing system , introduce run - time reconfiguration technique of fpga . with comparison of the common used dynamic communication network in parallel processor system , proposes the new dynamic reconfigurable multi - dsp system architecture based on run - time reconfigurable fpga
    第三章分析了多dsp并行系統(tǒng)體系結(jié)構(gòu)動(dòng)態(tài)可重構(gòu)的意義，介紹了fpga動(dòng)態(tài)配置技術(shù)，比較了現(xiàn)有的一些多處理器動(dòng)態(tài)互連的設(shè)計(jì)實(shí)現(xiàn)方法，在此基礎(chǔ)上，提出了利用局部動(dòng)態(tài)重構(gòu)fpga技術(shù)設(shè)計(jì)實(shí)現(xiàn)實(shí)時(shí)動(dòng)態(tài)可重構(gòu)多sharc功能系統(tǒng)的新方法。
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